P.M. Bangare
Assistant Professor, Department of Electronics and Telecommunication Engineering,
Sinhgad College of Engineering, Pune, Maharashtra, India
M.B. Mali
Professor and Head, Department of Electronics and Telecommunication Engineering,
Sinhgad College of Engineering, Pune, Maharashtra, India
ABSTRACT
To meet the challenging needs of user’s front-end industries are designing and progressively developing skilled architecture simulation, synthesis and implementation tools. However, in the electronics industry the major contribution of the affecting parameters like power utilization, resources required, area consumed, and frequency attained cannot be altered even after writing algorithms in most sophisticated forms. It has given birth to the reprogrammable devices like Field Programmable Gate Arrays (FPGA). For scheduling multiple tasks to allow multiple tasks to reconfigure in reconfigurable device is important. Scheduler is proposed to work with scheduling algorithm with provision of operating multiple tasks concurrently or on priority-based, routine tasks are executed on the ideal state of the higher priority tasks.
Keywords: dynamic scheduler, FPGA, reconfigurable device, micro-processor, FPT and SPt task handling
Cite this Article: P.M. Bangare, M.B. Mali. Dynamic Task Scheduler for Reconfigurable Devices. International Journal of Solid State Materials. 2020; 6(1): 24–32p.
Author Biographies
P.M. Bangare, Assistant Professor, Department of Electronics and Telecommunication Engineering,
Sinhgad College of Engineering, Pune, Maharashtra, India
Assistant Professor, Department of Electronics and Telecommunication Engineering,
Sinhgad College of Engineering, Pune, Maharashtra, India
M.B. Mali, Professor and Head, Department of Electronics and Telecommunication Engineering,
Sinhgad College of Engineering, Pune, Maharashtra, India
Professor and Head, Department of Electronics and Telecommunication Engineering,
Sinhgad College of Engineering, Pune, Maharashtra, India